Digital systems often rely on precise clocks for advancing states and data pipelines. Such precise clocks can be generated using crystal oscillators such as from a vibrating quartz crystal. The oscillating signal from the crystal can be applied to a phase-locked loop (PLL) to further refine the clock signal by reducing jitter and cycle-to-cycle variations.
Since clocks are so vital to many digital systems, a back-up or redundant oscillator may be used to supply a back-up clock in case of a failure of the primary oscillator. FIG. 1 shows a prior-art redundant clock source. Primary oscillator 10 generates a primary clock signal that is input to muxes 12, 22. Secondary oscillator 20 generates a second clock signal that is also input to muxes 12, 22.
In lock detector 62, phase detector 14 compares phases of the clock selected by mux 12 to the feedback clock from flip-flop 18. Phase mis-matches cause a voltage applied to a voltage-controlled oscillator (VCO) to vary. Third VCO 16 receives the phase-varying voltage from phase detector 14 and generates a clock that varies in frequency with the input voltage. The clock from third VCO 16 is input to flip-flop 18 to generate a clock that can be used by a system.
A second lock detector may also be present, although it is not always required. In second lock detector 64, phase detector 24 compares phases of the clock selected by mux 22 to the feedback clock from flip-flop 28. Fourth VCO 26 receives the phase-varying voltage from phase detector 24 and generates a clock that varies in frequency with the input voltage. The clock from fourth VCO 26 is input to flip-flop 28 to generate a clock that can be used by a system.
Control logic 70 can receive a clock-select signal from a system, or can be informed when a clock failure occurs. Control logic 70 then causes muxes 12, 22 to select the other clock source, such as the second clock from secondary oscillator 20 rather than the first clock from primary oscillator 10. Control logic 70 may be able to detect a clock failure by examining the varying voltages from phase detectors 14, 24, and may then switch clock sources.
While having a back-up clock source is useful, several oscillators may be needed by clock pulse generator 36. For example, at least 3 oscillators are needed. Two crystal oscillators are needed for primary oscillator 10 and for secondary oscillator 20, while a third oscillator is needed for third VCO 16, which locks to either primary oscillator 10 or to secondary oscillator 20.
When primary oscillator 10 fails, control logic 70 switches mux 12 to secondary oscillator 20. Since the varying voltage from phase detector 14 may take some time to decay, third VCO 16 can continue oscillating to generate the system clock when primary oscillator 10 fails and control logic 70 switches over mux 12 to secondary oscillator 20.
Oscillators can draw significant power and occupy a significant die or board area and can add to the expense of a system. Having three oscillators for the redundant clock generator is somewhat undesirable. It is preferable to have only 2 oscillators rather than 3 oscillators.
What is desired is a redundant clock generator that can switch-over to a back-up oscillator upon failure of a primary oscillator. A redundant clock generator that has only 2 oscillators is desirable.